In packet switching networks, routing is the process that directs or route the data packets depending on the destination address contained in each packet. During the process, router glance to a table (forwarding table) storing destination address of the incoming packet and takes out the information necessary to determine the path of the packets. The router architecture that is responsible for this is called Forwarding Plane or Data Plane or User Plane.
For a given system, virtual memory is divided in User Space and Kernel Space.
User space comprises the set of locations where normal user’s processes run. It has access to limited area of memory. Kernel is the core of operating system. It can access all the part of memory. Kernel exposes small part of kernel space to user space via an interface know as system calls. A typical x86 system has four rings of protection depending on privilege grants. They are kernel (Ring 0), VM hyper-visors (Ring 1), drivers (Ring 2) and application (Ring 3). Any code running on the system falls in one of the ring and hence gets privileged memory access depending on the ring.
Linux mainly uses Ring 0 and Ring 3. Ring 0 has access to all machine instructions while Ring 3 being the least privileged can only access to a subset of machine instructions.
DPDK or Data Plane Development Kit is a set of plane libraries and drivers for NIC – Network interface controller (Card necessary on a system to connect it to any network) for fast packet processing. It provides a programming framework (API) for x86, ARM and PowerPC processors and enables development of high speed data packet networking application. This is achieved as DPDK makes the data packets directly transfer from Network Controller (Hardware) to Applications (User space) and henceforth completely bypassing Kernel Space. Component of DPDK, EAL (Environment Abstraction Layer) makes this possible and hence it enables access of low-level resources like hardware and memory address.
Page table in operating systems are the data structures used by memory manager which contains the mapping of virtual addresses (used by processes) and physical addresses (used by RAM). TLB or Translation Look-aside Buffer is a cache which does the same job but only holds recently used pages with higher probability to be used again. It has size of about 12 to 4096 entries. When TLB misses the page CPU calls on page table to look into the page. DPDK uses very huge pages (upto 1GB), this makes more TLB hits and page miss replacement (from secondary memory) is reduced.
Data transmission rate is between DRAM (Dynamic-RAM) and memory controller enhanced using multi-channel memory architecture. Memory Manager of DPDK makes transmission through different channels uniform. It also keep a Ring to keep track of used and free objects.
Lock-less programming is the concept when code includes multi threading and these threads have shared memory but the threads can’t block each other or in other words there is no mutexes or locks. Queue Manager of DPDK uses this concept to manage buffers (viz. incoming packet queues , outgoing packet queues ) which are of fixed size and preallocated by buffer manager.
Control Plane is the component of network architecture which makes the decision about where traffic is sent. It is responsible for system configuration and management and draws the network topology. It builds information from ARP (Address Resolution Protocol), routing protocols and hence MAC learning from IP address and stores information in forwarding tables which makes forwarding decisions for data plane through forwarding path. In DPDK, control plane information is stored in hash table. This further reduces the time complexity of the process.